Reconfigurable Architecture Design: An Optimization Approach
Lead Research Organisation:
Imperial College London
Department Name: Electrical and Electronic Engineering
Abstract
This proposal is concerned with the automatic design of reconfigurable architectures. The proposed approach forms a radical departure from standard industrial and academic practice in reconfigurable architecture design. The main feature of this approach is its basis in formal global optimization proceduresfrom the mathematical programming and operations research communities, in contrast to the empirical approaches typically used to attack this problem.The intention is to develop and extend mathematical models of power consumption, computation throughput, and silicon area usage, and incorporate these within a mathematical programming framework. This will allow the simultaneous optimization of multiple architectural and synthesis parameters, leading to provable-quality solutions, and eliminating the dependence of the resulting architecture on heuristic bias.Promising preliminary results have already been achieved, providing provably optimal bounds on the relative computational speed of various DSP benchmarks compared to ASIC implementations of the same circuits, and proposing architectures resulting in up to 20% speed improvement (for the same area) or 60% area reduction (for the same speed) over commercial architectures.Funding is requested for a post-doctoral research associate (3 years) and a Ph.D. student (3.5 years) to work with the investigators.
Publications
Campregher N
(2006)
Yield enhancements of design-specific FPGAs
Guan Z
(2014)
Classification on variation maps: a new placement strategy to alleviate process variation on FPGA
in IEICE Electronics Express
Jamieson P
(2009)
An energy and power consumption analysis of FPGA routing architectures
Kahoul A
(2009)
Reconfigurable Computing: Architectures, Tools and Applications
Kahoul A
(2010)
Efficient Heterogeneous Architecture Floorplan Optimization using Analytical Methods
in ACM Transactions on Reconfigurable Technology and Systems
Morris G
(2007)
ROM to DSP block transfer for resource constrained synthesis
in IET Computers & Digital Techniques
Roldao A
(2010)
A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementation for Dense Matrices
in ACM Transactions on Reconfigurable Technology and Systems
Smith A
(2008)
Integrated Floorplanning, Module-Selection, and Architecture Generation for Reconfigurable Devices
in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Description | That formal mathematical optimization techniques can be used to identify promising regions of the reconfigurable architecture design space |
Exploitation Route | By the embedded computer architecture industry when trying to develop new architectures |
Sectors | Digital/Communication/Information Technologies (including Software),Electronics |
Description | In presentations to the reconfigurable computing industry |
First Year Of Impact | 2006 |
Sector | Digital/Communication/Information Technologies (including Software),Electronics |
Impact Types | Economic |
Description | Altera - Optimal Architectures |
Organisation | Altera |
Department | Altera Europe |
Country | United Kingdom |
Sector | Private |
PI Contribution | Publications |
Collaborator Contribution | Tools |
Impact | Publications |
Start Year | 2006 |
Description | Panasonic - Optimal Archs |
Organisation | Panasonic Industrial Europe GmbH (UK) |
Country | United Kingdom |
Sector | Private |
PI Contribution | Research Output |
Collaborator Contribution | Staff time |
Impact | Publications |
Start Year | 2006 |
Description | Xilinx - Optimal Archs |
Organisation | Xilinx Corp |
Country | United States |
Sector | Private |
PI Contribution | Research output |
Collaborator Contribution | Tools and devices |
Impact | Publications |
Start Year | 2006 |