Synthesis and Optimisation of Designs Based on Novel Canonical Algebraic Structures
Lead Research Organisation:
University of Bristol
Department Name: Computer Science
Abstract
Behavioral synthesis, an important part of Electronic System Level (ESL)design, provides the most effective means to optimize the design by allowingthe designer to concentrate on the highest level of design abstraction, namely behavioral and algorithmic levels. Behavioral synthesis has unquestionably the greatest impact on the quality of complex Integrated Circuits (ICs) and systems on chip (SoC) designed with CAD tools. Despite many advances in behavioral synthesis over the past two decades, existing synthesis systems are still ineffective in translating the initial design specification into hardware.In particular, existing tools rely on a single, fixed data flow graph (DFG), extracted from the design specification, and mapped onto hardware.This research proposes a systematic approach to behavioral synthesis based on functional (rather than structural) representation of the computation. In particular, a new method is proposed to perform efficient factorization and decomposition for polynomial expressions derived from algorithmic design descriptions using two novel, canonical algebraic structures:1) Taylor Expansion Diagram (TED), and2) Galois Field Decision Diagrams (GPDD).As canonical representations, these structures can capture an entire class of structural solutions, rather than a single DFG obtainable with current methods. Through a set of novel functional decomposition procedures proposed in this research, the initial functional representation can be converted into a set of structural representations (data flow graphs, DFG), from which an optimum one can be chosen for a particular design objective, such as thecircuit area, latency, power, or performance, leading to efficient hardware implementations.The proposed method will equip the designers with a tool to perform efficient exploration of architectural solutions, without a need to rewrite and re-synthesize the original specification in search for the best solution.
Organisations
Publications
Mathew J
(2011)
Pseudo-Parallel Datapath Structure for Power Optimal Implementation of 128-pt FFT/IFFT for WPAN
in Circuits, Systems, and Signal Processing
Shafik R
(2015)
A Low-Cost Unified Design Methodology for Secure Test and Intellectual Property Core Protection
in IEEE Transactions on Reliability
Kavousianos X
(2011)
Defect-Oriented LFSR Reseeding to Target Unmodeled Defects Using Stuck-at Test Sets
in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Rahaman H
(2010)
Test Generation in Systolic Architecture for Multiplication Over $GF(2 ^{m})$
in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hosseinabady M
(2011)
Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph
in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Mathew J
(2010)
A Galois field-based logic synthesis with testability
in IET Computers & Digital Techniques
Mishra V
(2011)
Fault-tolerant de-Bruijn graph based multipurpose architecture and routing protocol for wireless sensor networks
in International Journal of Sensor Networks
Sun L
(2014)
Design and Analysis of Binary Tree Static Random Access Memory for Low Power Embedded Systems
in Journal of Low Power Electronics
Bandan M
(2014)
Energy Efficient Lifetime Reliability-Aware Checkpointing for Real-Time System
in Journal of Low Power Electronics
Banerjee S
(2011)
A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization
in Journal of Low Power Electronics
Description | Project developed generalized theory and an efficient graph-based technique for the calculation and representation of coefficients of multivariate canonic polynomials over arbitrary finite fields in any polarity. The technique presented for computing coefficients is unlike polynomial interpolation or matrix-based techniques and takes into consideration efficient graph-based forms which can be available as an existing resource during synthesis, verification, or simulation of digital systems. |
Exploitation Route | Techniques for optimization of the graph-based forms for representing the coefficients are to be extended |
Sectors | Education,Electronics,Security and Diplomacy |