High permittivity dielectrics on Ge for end of Roadmap application
Lead Research Organisation:
Liverpool John Moores University
Department Name: Engineering Tech and Maritime Operations
Abstract
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Publications
Lin L
(2011)
A Single Pulse Charge Pumping Technique for Fast Measurements of Interface States
in IEEE Transactions on Electron Devices
Tang BJ
(2011)
Abnormal VTH/VFB shift caused by as-grown mobile charges in Al2O3 and its impacts on Flash
in Technical Digest of the International Electron Devices Meeting (IEDM)
Ji Z
(2012)
A New Mobility Extraction Technique Based on Simultaneous Ultrafast $I_{d}$-$V_{g}$ and $C_{\rm cg}$-$V_{g}$ Measurements in MOSFETs
in IEEE Transactions on Electron Devices
Duan M
(2012)
Defect Loss: A New Concept for Reliability of MOSFETs
in IEEE Electron Device Letters
Zhang, J. F.
(2012)
Development of New Characterisation Technique for Interface States Beyond Bandgap
in 2012 Ieee 11th International Conference on Solid-State and Integrated Circuit Technology (Icsict-2012)
Benbakhti B
(2012)
Characterization of Electron Traps in Si-Capped Ge MOSFETs With $\hbox{HfO}_{2}/\hbox{SiO}_{2}$ Gate Stack
in IEEE Electron Device Letters
Baojun Tang
(2012)
Investigation of Abnormal $V_{\rm TH}/V_{\rm FB}$ Shifts Under Operating Conditions in Flash Memory Cells With $ \hbox{Al}_{2}\hbox{O}_{3}$ High-$\kappa$ Gate Stacks
in IEEE Transactions on Electron Devices
Ji Z
(2012)
Interface States Beyond Band Gap and Their Impact on Charge Carrier Mobility in MOSFETs
in IEEE Transactions on Electron Devices
Tang B
(2013)
Statistical characterization of vertical poly-Si channel using charge pumping technique for 3D flash memory optimization
in Microelectronic Engineering
Liu W
(2013)
Observation of the Ambient Effect in BTI Characteristics of Back-Gated Single Layer Graphene Field Effect Transistors
in IEEE Transactions on Electron Devices
Description | The key findings of this project upto now include: (1) The capture cross sections of electron traps are determined; (2) An energy switching model has been proposed for hole traps; (3) The energy profile of hole traps has been extracted; (4) Mechanism for the differences in NBTI under DC and AC stresses has been clarified; (5) The sources for defects have been identified. (6) Based on the above, a technique for predicting the BTI lifetime under both DC and AC stresses has been proposed and testified against experimental data. |
Exploitation Route | Potential use includes: (i) Assess the PBTI device lifetime under both DC and AC stresses for Ge nMOSFETs; (ii) Assess the NBTI device lifetime under both DC and AC stresses for Ge pMOSFETs; (iii) Process optimization by suppressing defects through controlling the identified sources. (iv) Modelling the device degradation in circuits using Ge MOSFETs. Exploitation routes are: (i) Non-academic project partners; (ii) International conferences. |
Sectors | Digital/Communication/Information Technologies (including Software),Education,Electronics |
Description | 1. The BTI lifetime prediction method has been used in the qualification of the Ge processes. 2. The sources of defects identified have been used in assisting process optimization. 3. The PI has been invited to deliver short courses on Bias Temperature Instability modelling. |
First Year Of Impact | 2019 |
Sector | Digital/Communication/Information Technologies (including Software),Education,Electronics |
Impact Types | Economic |