Models and Methodologies for Embedded Real-time System Design

Lead Research Organisation: University of York
Department Name: Computer Science

Abstract

Over the last few decades the development of software engineering tools has transformed the field. The same has not happened in embedded systems and there has been little advancement in some design processes since the 1970's. My research aims to create new tools, frameworks and processes for the development of embedded systems and embedded software that moves forward the creation process towards a higher level of abstraction. The potential impact of work like this is limitless and could lead to a revolution in the design of embedded systems, which has benefits not only to research but education and industry alike.

Publications

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Studentship Projects

Project Reference Relationship Related To Start End Student Name
EP/N509802/1 01/10/2016 31/03/2022
1796038 Studentship EP/N509802/1 01/10/2016 30/09/2019 Jonathan Rainer
 
Description Caches are like a table in a library, rather than having to go and search for each book every time you want to look something up you can keep books you need a lot on your table. This reduces how long it takes you to look for information. Caches do this for processors, and my research has focussed on how we can make it so that they keep information that is referenced a lot for longer while jettisoning information that is not. My research has shown that there is some evidence that by recording the actions taken by a processor when there is no cache, and then giving that information to the cache while it's running can significantly reduce the runtime of the system. However there are a lot of overheads this process introduces that would need to be tackled before this could become a product that could be used commercially and the implementation would need to be further optimised.
Exploitation Route There are several key outcomes that could be developed, the system used to capture information about the running program could easily be adapted and advanced if someone wanted to consider a way of tracking runtime metrics about a cache or system. Further if someone wanted to develop Trace Assisted Caching further they could do, taking the hardware designs I have contributed and optimising them to remove some of the overheads the techniques introduce. Further there are many applications to High Performance Computing and Out-of-Order processors that are explored in the outcomes section of the Thesis.
Sectors Aerospace, Defence and Marine,Digital/Communication/Information Technologies (including Software),Electronics
 
Title Experimental Data (Including Hardware Variants) Measuring Memory Activity for Trace Assisted Caching 
Description As part of the Thesis "Using Tracing to Enhance Data Cache Performance in CPUs" experiments were conducted to record all the memory activity seen during the runs of different benchmarks running on a CPU configured with different varieties of cache. The five variants encompassed a processor with no cache, an 8-way Set-Associative Cache, a Direct-Mapped Cache and then a new Trace Assisted Cache in both Direct-Mapped and Set Associative variants. The intent was to provide more insight into the exact operation of memory during the benchmark's execution. The files contained in this submission include all the files that were generated during the experiments as well as the final dataset this produced. Included in the *.tar.xz file is a set of directories organised into folders for each combination of benchmark and hardware variant. Each folder is labelled __mg so fac_nc_mg means the fac benchmark run on the hardware that had No Cache. Any hardware variant that begins cc stands for complex cache and refers to the Trace Assisted Versions. Inside these folders are contained the compiled executables and linker files that were used, all of the code generated by the automation framework, the Vivado project that was created to enable the hardware to be synthesised, any bitfiles generated by this process and the resulting vcd files from which the data in the CSV files was extracted. The csv files are organised also by benchmark and hardware variant and are organised in the same way as the experiment files. The data in the CSV files is designed to be read in by Sawatari to produce Memory Activity Diagrams. Vivado 2018.2 was used to create the bitfiles and so that version or higher would be required to open the files. Also as a warning, when expanded the experiments archive is over 50GB in size so please be aware of this when downloading. 
Type Of Material Database/Collection of data 
Year Produced 2020 
Provided To Others? Yes  
Impact None as yet 
URL https://zenodo.org/record/4042892
 
Title Experimental Data (Including Hardware Variants) Measuring Runtime for Trace Assisted Caching 
Description As part of the Thesis "Using Tracing to Enhance Data Cache Performance in CPUs" experiments were conducted to measure the runtime of different benchmarks running on a CPU configured with different varieties of cache. The five variants encompassed a processor with no cache, an 8-way Set-Associative Cache, a Direct-Mapped Cache and then a new Trace Assisted Cache in both Direct-Mapped and Set Associative variants. The intent was to measure whether adding the Trace Assistance to the cache would significantly reduce runtime. The files contained in this submission include all the files that were generated during the experiments as well as the final dataset this produced. Included in the *.tar.xz file is a set of directories organised into folders for each combination of benchmark and hardware variant. Each folder is labelled _ so fac_nc means the fac benchmark run on the hardware that had No Cache. Any hardware variant that begins cc stands for complex cache and refers to the Trace Assisted Versions. Inside these folders are contained the compiled executables and linker files that were used, all of the code generated by the automation framework, the Vivado project that was created to enable the hardware to be synthesised, any bitfiles generated by this process and the resulting vcd files from which the data in the XLS file was extracted. Vivado 2018.2 was used to create the bitfiles and so that version or higher would be required to open the files. Also as a warning, when expanded the experiments archive is over 100GB in size so please be aware of this when downloading. The XLSX file contains the measured results, split by benchmark and hardware and is provided as a summary of the vast quantities of data included in the archive. 
Type Of Material Database/Collection of data 
Year Produced 2020 
Provided To Others? Yes  
Impact None as yet 
URL https://zenodo.org/record/4040337
 
Title Ichijou - Automation Framework for Kuuga 
Description Ichijou uses Kuuga and instruments it via Python scripts to produce the data required to analyse the runtimes of the individual hardware variants. 
Type Of Material Data analysis technique 
Year Produced 2020 
Provided To Others? Yes  
Impact None as yet 
URL https://github.com/jonathanrainer/Ichijou
 
Title Kuuga - Hardware Implementation of Trace Assisted Caching Platform 
Description Kuuga is a hardware platform that demonstrates Trace Assisted Caching at work. It allows you to swap out the cache implementation and provides Set-Associative and Direct Mapped versions. 
Type Of Material Computer model/algorithm 
Year Produced 2020 
Provided To Others? Yes  
Impact None as yet 
URL https://github.com/jonathanrainer/Kuuga/tree/v1.0
 
Title Sawatari - Memory Access Time Analysis for Kuuga 
Description Sawatari allows us to visualise the memory access patterns for Kuuga so it's possible to analyse the exact patterns that show up for periods of activity and inactivity. This tool automates the capture and plotting of those measures. 
Type Of Material Data analysis technique 
Year Produced 2020 
Provided To Others? Yes  
Impact None as yet 
URL https://github.com/jonathanrainer/Sawatari/tree/v1.0