Acceleration of trigger algorithms with FPGAs at the LHC implemented using higher-level programming languages
Lead Research Organisation:
Imperial College London
Department Name: Physics
Abstract
The goal of the PhD project is to facilitate development and implementation of triggering at the LHC by introducing a new key technology: higher-level programmable dataflow engines. The project will be conducted in close collaboration with Maxeler Technologies, London, the pioneer and leader in development of dataflow computing engines.
The LHC collides protons at a rate of 40 MHz, however "interesting" events, such as those containing the Higgs boson, occur far less frequently. It is technologically infeasible to retain every event and so events must be analysed in real time to select only the "interesting" ones from the very large background. To do this, CMS uses a trigger system. The second tier of the trigger system, the Higher-Level Trigger (HLT) is based on a farm of 30 000 CPU cores.
The LHC will be upgraded over the next five years or so to deliver a higher proton-proton interaction rate. This presents an unprecedented challenge to the real-time data processing of the CMS HLT, requiring processing power orders of magnitude larger than today. This exceeds by far the expected increase in processing power for conventional CPUs from Moore's Law, demanding an alternative approach.
This project will study the feasibility of allowing the CMS HLT applications to run on heterogeneous hardware, Maxeler's dataflow engines, with the goal of demonstrating that they can achieve higher throughput and better energy efficiency by running each step of a computing task on the architecture that best matches its characteristics. FPGAs are an excellent candidate to solve this problem, offering high throughout and low power consumption, making them cost effective, however the difficulty in programming FPGAs in low-level languages has resulted in this technology being over-looked until now.
London-based Maxeler Technologies is the world leader in the development and application of FPGA-based dataflow computing engines for high-performance computing (HPC). Maxeler has created a first-of-its-kind higher-level programming environment for FPGA-based computers that eliminates the need to program the FPGAs using low-level languages, making the technology fully accessible to scientists.
The project builds on a highly successful previous CASE studentship collaboration between Imperial and Maxeler (ST/L002728/1). The previous project demonstrated the applicability of Maxeler's high-level programming approach in low-latency data processing environments and also took the first steps into the use of Maxeler's development environment and hardware in accelerating trigger algorithms and implementing Machine Learning algorithms in FPGAs.
This project aims to demonstrate that triggering algorithms written using Maxeler's programming environment can meet the stringent timing requirements faced in the CMS trigger. Imperial will work with Maxeler to further optimise their programming environment for the implementation of triggering algorithms and study the performance improvement to the Higher-Level Trigger offered by Maxeler's dataflow computing technology. Various approaches to the implementation of sophisticated algorithms, including Machine Learning, in FPGAs will be explored, addressing a key need for many data-processing aspects of the STFC science programme.
The LHC collides protons at a rate of 40 MHz, however "interesting" events, such as those containing the Higgs boson, occur far less frequently. It is technologically infeasible to retain every event and so events must be analysed in real time to select only the "interesting" ones from the very large background. To do this, CMS uses a trigger system. The second tier of the trigger system, the Higher-Level Trigger (HLT) is based on a farm of 30 000 CPU cores.
The LHC will be upgraded over the next five years or so to deliver a higher proton-proton interaction rate. This presents an unprecedented challenge to the real-time data processing of the CMS HLT, requiring processing power orders of magnitude larger than today. This exceeds by far the expected increase in processing power for conventional CPUs from Moore's Law, demanding an alternative approach.
This project will study the feasibility of allowing the CMS HLT applications to run on heterogeneous hardware, Maxeler's dataflow engines, with the goal of demonstrating that they can achieve higher throughput and better energy efficiency by running each step of a computing task on the architecture that best matches its characteristics. FPGAs are an excellent candidate to solve this problem, offering high throughout and low power consumption, making them cost effective, however the difficulty in programming FPGAs in low-level languages has resulted in this technology being over-looked until now.
London-based Maxeler Technologies is the world leader in the development and application of FPGA-based dataflow computing engines for high-performance computing (HPC). Maxeler has created a first-of-its-kind higher-level programming environment for FPGA-based computers that eliminates the need to program the FPGAs using low-level languages, making the technology fully accessible to scientists.
The project builds on a highly successful previous CASE studentship collaboration between Imperial and Maxeler (ST/L002728/1). The previous project demonstrated the applicability of Maxeler's high-level programming approach in low-latency data processing environments and also took the first steps into the use of Maxeler's development environment and hardware in accelerating trigger algorithms and implementing Machine Learning algorithms in FPGAs.
This project aims to demonstrate that triggering algorithms written using Maxeler's programming environment can meet the stringent timing requirements faced in the CMS trigger. Imperial will work with Maxeler to further optimise their programming environment for the implementation of triggering algorithms and study the performance improvement to the Higher-Level Trigger offered by Maxeler's dataflow computing technology. Various approaches to the implementation of sophisticated algorithms, including Machine Learning, in FPGAs will be explored, addressing a key need for many data-processing aspects of the STFC science programme.
People |
ORCID iD |
| Alexander Tapper (Primary Supervisor) | |
| Liv VAGE (Student) |