Hard-Middleware: Facilitating Reliable Machine Learning Deployment for Automotive Applications

As transistor scaling continues to push for greater performance and energy efficiency, the susceptibility of electronic devices to atmospheric radiation is of greater concern. Such radiation can cause failure within a device. The reliability of a system is of increasing consideration, especially for safety-critical applications such as autonomous driving. These safety-critical applications, particularly in the automotive sector, often feature machine learning tasks, such as object detection. Performance and reliability requirements of such applications are varied and often change over time.
Normally, applications are accelerated through the translation of general-purpose hardware (software) to bespoke circuitry (hardware). This can provide huge speed-ups over conventional software-based approaches. One such class of platforms for custom hardware that is of growing interest in the automotive sector are FPGAs (Field-Programmable Gate Arrays). This type of platform allows users to exploit the benefits of custom hardware without the large non-recurring engineering cost of producing custom silicon.
Radiation can cause numerous problems on FPGAs. Effects such as TID (Total Ionising Dose), high energy particles that causes circuit-level damage, have been vastly reduced using radiation-hardened devices. However, the effects of SEUs (Single Event Upsets), high-energy particles that cause the logical state of a memory cell to flip, must be handled using SEU mitigation techniques.
We propose the creation of a virtual hardware, or overlay, dubbed "Hard-Middleware" to act as an intermediary between the user's application and the FPGA platform it will execute on. Rather than programming the FPGA directly, we propose the targeting of this virtual hardware. The overlay will then be realised on physical hardware. This will allow the architecture to adapt dynamically to changing application requirements and environmental conditions.
Performance and efficiency can then be balanced with reliability without affecting the design of the application. The user can then specify qualities of service that the overlay will then deliver. For a given application, the reliability requirements can be considered separately and transparently. The overlay will utilise existing hardening methodologies to realise the required level of reliability for a given application.
CGRAs (Coarse Grain Reconfigurable Arrays) are a middle ground between general-purpose processors and bespoke custom circuitry. Hardware is organised into an array of processing elements that can perform word-level operations, compared with FPGAs bit-level operations. Due to the coarse-grained nature of the compute units, a CGRA can be configured much faster than an FPGA.
We will use a CGRA as our virtual hardware. The user will target this architecture at a higher level, while the architecture itself will be mapped to an FPGA at a low-level. Protection mechanisms will be provided between the CGRA and the FPGA, meaning that the user need only map their application to the CGRA. Using this type of architecture allows us to draw on the pre-existing research that has focused on the development of CGRAs and focus our efforts on providing an automatic performance-reliability trade-off that the user need not consider in detail.
Enabling the deployment of modern machine learning applications in the automotive sector will facilitate a step change in the capability of autonomous driving systems. Although our research focuses on the automotive sector, it will be of wider benefit to the continuation of high-reliability computation in the face of increasingly unreliable hardware.