Enabling FPGAs in new HPC heterogeneous systems through dataflow abstractions and enhanced flexibility

Scientific computing makes extensive use of the very large collections of hardware resources found in
HPC systems. The ever growing demand of this domain requires the search of new strategies to deal with
increasing amounts of data in feasible time to solution. One of these strategies is the use of FPGAs, since their
reconfigurability allows them to overcome some of the limitations faced by the traditional HPC hardware. However, programming them
requires specific knowledge foreign to HPC software developers and they are also very rigid, which hinders their integration in HPC
systems.

Our hypothesis is that improved tooling for FPGAs with HPC workloads in mind will result in the technology better suiting supercomputing.
To answer this research question we focus both on the issues of performance and flexibility. The architecture of the FPGA maps better to a
dataflow approach than the traditional programming languages. Hence, we are exploring the performance improvements provided by a dataflow layer
exposed to the programmer. At the same time, we are looking into how advanced reconfiguration techniques help dynamic management of the workloads
on FPGA and allow to overcome their native rigidity.