ROM to DSP block transfer for resource constrained synthesis (2007)
Attributed to:
Reconfigurable Architecture Design: An Optimization Approach
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1049/iet-cdt:20060016
Publication URI: http://dx.doi.org/10.1049/iet-cdt:20060016
Type: Journal Article/Review
Parent Publication: IET Computers & Digital Techniques
Issue: 1