Classification on variation maps: a new placement strategy to alleviate process variation on FPGA (2014)
Attributed to:
Reliable Numerical Computation with Parallel Unreliable Technologies
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1587/elex.10.20130912
Publication URI: http://dx.doi.org/10.1587/elex.10.20130912
Type: Journal Article/Review
Parent Publication: IEICE Electronics Express
Issue: 3