VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases

First Author: Rahaman H
Attributed to:  Synthesis and Optimisation of Designs Based on Novel Canonical Algebraic Structures funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1007/978-3-642-31494-0_30

Publication URI: http://dx.doi.org/10.1007/978-3-642-31494-0_30

Type: Book Chapter

Book Title: Progress in VLSI Design and Test (2012)

Page Reference: 258-269

ISBN: 978-3-642-31493-3

ISSN: 1388-1957