Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph (2011)

First Author: Hosseinabady M
Attributed to:  Synthesis and Optimisation of Designs Based on Novel Canonical Algebraic Structures funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/tvlsi.2010.2050914

Publication URI: http://dx.doi.org/10.1109/tvlsi.2010.2050914

Type: Journal Article/Review

Parent Publication: IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue: 8