BCH code based multiple bit error correction in finite field multiplier circuits (2011)

First Author: Poolakkaparambil M
Attributed to:  Synthesis and Optimisation of Designs Based on Novel Canonical Algebraic Structures funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/isqed.2011.5770792

Publication URI: http://dx.doi.org/10.1109/isqed.2011.5770792

Type: Conference/Paper/Proceeding/Abstract

ISBN: 978-1-61284-913-3