Test Generation in Systolic Architecture for Multiplication Over $GF(2 ^{m})$ (2010)

First Author: Rahaman H
Attributed to:  Synthesis and Optimisation of Designs Based on Novel Canonical Algebraic Structures funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/tvlsi.2009.2023381

Publication URI: http://dx.doi.org/10.1109/tvlsi.2009.2023381

Type: Journal Article/Review

Parent Publication: IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue: 9