Speedup and Parallelization Models for Energy-Efficient Many-Core Systems Using Performance Counters (2017)

First Author: Al-Hayanni M
Attributed to:  PRiME: Power-efficient, Reliable, Many-core Embedded systems funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/hpcs.2017.68

Publication URI: http://dx.doi.org/10.1109/hpcs.2017.68

Type: Conference/Paper/Proceeding/Abstract