Low Latency Parallel Schedulers for Photonic Integrated Optical Switch Architectures in Data Centre Networks (2017)
Attributed to:
Breaking the Copper Bottleneck: Computer Architecture and Power Implications of Photonic Interconnect
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1109/ecoc.2017.8345961
Publication URI: http://dx.doi.org/10.1109/ecoc.2017.8345961
Type: Conference/Paper/Proceeding/Abstract