Verifiable Code Generation from Scheduled Event-B Models

First Author: Dalvandi M
Attributed to:  PRiME: Power-efficient, Reliable, Many-core Embedded systems funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1007/978-3-319-91271-4_16

Publication URI: http://dx.doi.org/10.1007/978-3-319-91271-4_16

Type: Book Chapter

Book Title: Abstract State Machines, Alloy, B, TLA, VDM, and Z (2018)

Page Reference: 234-248