Fortran High-Level Synthesis: Reducing the Barriers to Accelerating HPC Codes on FPGAs (2023)

First Author: Rodriguez-Canal G

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/fpl60245.2023.00010

Publication URI: http://dx.doi.org/10.1109/fpl60245.2023.00010

Type: Conference/Paper/Proceeding/Abstract