Hardware Acceleration for Machine Learning (2017)
Attributed to:
Event-based parallel computing - partially ordered event-triggered systems (POETS)
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1109/isvlsi.2017.127
Publication URI: http://dx.doi.org/10.1109/isvlsi.2017.127
Type: Conference/Paper/Proceeding/Abstract
ISSN: 21593477 21593469