Area efficient asynchronous SDM routers using 2-stage Clos switches (2012)
Attributed to:
Energy Efficient Networks-on-Chip for Dynamically Reconfigurable Computing Platforms.
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1109/date.2012.6176710
Publication URI: http://dx.doi.org/10.1109/date.2012.6176710
Type: Conference/Paper/Proceeding/Abstract
ISBN: 978-1-4577-2145-8