Verilog-A Based Effective Complementary Resistive Switch Model for Simulations and Analysis (2014)

First Author: Yang Y
Attributed to:  Yield and reliability enhancement techniques for novel memory devices funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/les.2013.2278740

Publication URI: http://dx.doi.org/10.1109/les.2013.2278740

Type: Journal Article/Review

Parent Publication: IEEE Embedded Systems Letters

Issue: 1