Variation-Adaptive Design in FPGAs
Lead Research Organisation:
Imperial College London
Department Name: Electrical and Electronic Engineering
Abstract
This proposal is concerned with design techniques to compensate for parametric variations in deep-submicron configurable digital circuits. The growth of the microelectronics industry over the last four decades has been based on reducing the size of transistors to make integrated circuits smaller, faster and less expensive. The benefits obtained by transistor scaling are now diminishing as it becomes increasingly difficult to control the spread of parameters within a single chip.The research in this proposal will investigate new variation-aware design techniques in deep-submicron programmable logic devices. This is well-aligned with the recently developed Microelectronics Grand Challenges'' roadmap, particularly GC3---Moore for Less''. The premise for the research is that a single design can be implemented in more than one way in a given programmable logic device. In the presence of variations, distinct implementations will exhibit different performances, although they are functionally identical.The intention is to discover and develop strategies which exploit this feature in existing programmable logic devices. Furthermore, architectural modifications to such devices will be proposed to increase the obtainable benefit. These goals will be achieved from a thorough analysis of the nature of parametric variability from empirical studies, followed by the rigorous use of probabilistic modelling and optimisation theory.
Publications
Stott E
(2013)
Variation and Reliability in FPGAs
in IEEE Design & Test
Stott E
(2010)
Degradation in FPGAs
Stott E
(2011)
Improving FPGA Reliability with Wear-Levelling
Stott E
(2010)
Degradation Analysis and Mitigation in FPGAs
Stott E
(2010)
Fault tolerance and reliability in field-programmable gate arrays
in IET Computers & Digital Techniques
Stott E
(2014)
Timing Fault Detection in FPGA-Based Circuits
Description | New method to measure delay both online and offline. This results are the foundation of the EPSRC Programme Grant PRiME (EP/K034448/1). |
Exploitation Route | In addition to PRiME project, our method has also been used by groups around the world including U. Penn (DeHon), U. Sydney (Leong) |
Sectors | Digital/Communication/Information Technologies (including Software) Electronics |
URL | http://www.prime-project.org/2014/10/09/dvfs-demo/ |
Description | Altera |
Organisation | Altera |
Country | United States |
Sector | Private |
PI Contribution | The research from the project has been followed up by Altera in investigating the impact of variation in FPGA to their future family. We have shared our results with their staff, in particular with Altera Fellow, Dr David Lewis. |
Collaborator Contribution | Altera provided us with hardware boards, FPGA chips and also they shared with us their confidential internal results on their measure variation data. |
Impact | Outcome includes a granted patent: P.Y.K. Cheung, N. P. Sedcole, and J. S. J. Wong. Method of measuring delay in an integrated circuit, Oct. 8 2013. US Patent 8,552,740. |
Start Year | 2010 |
Description | Maxeler |
Organisation | Maxeler Technologies Inc |
Department | Maxeler Technologies |
Country | United Kingdom |
Sector | Private |
PI Contribution | We have assigned three of our patents to Maxeler: US6369610, US7543283, US12/747650 |
Collaborator Contribution | They have provide us with hardware and software donations to support our projects. |
Impact | Impact as granted patents: US6369610, US7543283, US12/747650 |
Start Year | 2010 |
Title | METHOD OF MEASURING DELAY IN AN INTEGRATED CIRCUIT |
Description | A method of measuring signal delay in a integrated circuit comprising applying a common clock signal at a circuit input and output, applying a test signal at the circuit input, detecting a corresponding output signal at the circuit output and detecting whether the test signal and output signal occur in a common part of the clock signal. |
IP Reference | US2011095768 |
Protection | Patent granted |
Year Protection Granted | 2011 |
Licensed | Yes |
Impact | New methodology for measurement used by many. |