Programmable Fabrics and Spatial Compilers

Advances in fabrication technology will soon provide computer architects with an almost limitless supply of transistors. This technology scaling could permit thousands of individual processor cores to be integrated onto a single chip. In fact, many assume that these ``manycore architectures offer a panacea in terms of performance and scalability. Unfortunately, roadmaps built upon such an assumption often fail to consider the fundamental shift in design trade-offs that will take place in the longer term. It is the goal of this project to use a far more open-ended strategy to explore viable processor designs. We aim to investigate how key features of ASIC, FPGA and multicore approaches can be combined to produce the most apposite architectures. We call solutions from this region of the architectural design space programmable fabrics . These will be targeted by novel compilers with the ability to optimise program execution under a range of physical constraints. Unlike compilers for centralised uniprocessors, we expect to incorporate features from logic synthesis and place-and-route tools. The aim of this proposal is to highlight the need to explore longer term limits to performance and to evaluate a family of potential architectural solutions.