Dynamic Adaptation in Heterogeneous Multicore Embedded Processors

The overall objective of this project is to investigate new and novel methods of automating the design, of both the hardware and software, of embedded systems to enable the timely creation of future generations of high-performance low-power digital appliances. This is a vertically-integrated project, which brings together research in compilers, architectures, signal processing, and an economically-important emerging application area.Embedded processors are an integral part of our everyday lives; from smart phones and flash memory sticks, to wireless communications, automotive computing, bio-medical devices, and many more. Future embedded processors will require significantly higher performance than the processors we have today. However, this must be achieved whilst also increasing their energy efficiency, as such systems are increasingly used in mobile or battery-operated devices.Performance cannot be increased simply by clocking devices at a higher frequency, as this significantly reduces energy efficiency.Previous research has shown that customizing a processor according to its application can provide a significant performance boost whilst simultaneously reducing energy consumption. Similarly, the use of multi-core processors, which can be specialized in heterogeneous ways, offers additional performance in a more energy-efficient way than can be achieved simply by the homogeneous replication of a fixed processor.The first challenge with application-specific processors, which is compounded in heterogeneous multi-core systems, is the vast array of possible designs from which to choose. This increasing complexity of the design space of computer systems, coupled with the drive for lower energy consumption, means that manual approaches to design are no longer feasible. Instead, by automating the process of searching the design space, it becomes possible to find the best designs. However, this approach is computationally intractable, due to the sheer number of designs that must be considered. There is now strong evidence, from our prior work and from others, that machine learning can provide a fast track to design-space exploration in both processor design and compiler design.The second challenge addressed by this project is variability in behaviour. For example, a broadband modem may wish to adapt its behaviour to the environmental conditions affecting signal quality. At the silicon level, factors such as temperature, process variation and operating voltage will affect the performance and energy consumption of the device. Devices that are able to adapt their hardware and software behaviour to meet these changing circumstances will not be constrained by worst-case analysis at design time, but will be able to tune their behaviour dynamically to meet actual real-time constraints. It is widely accepted that variability is a growing concern that requires a new approach. This project examines how dynamic adaptation in software and hardware can solve this problem. This will involve a combination of just-in-time compilation, to create more dynamic software, as well as just-in-time instruction set re-synthesis, to create dynamic processors.A key aspect of this project is the synergy between new design methods and an emerging application; in this case LED-based Visible Light Communication (VLC). The use of LED lighting is growing rapidly, due its low energy consumption. LED light can also be modulated to carry a digital payload at speeds even higher than 100 Mbps. However, this presents a major computational challenge, which we aim to address using the dynamically adaptable customized multi-core processors and compilers outlined above. We aim to extend the use of machine learning from off-line (i.e. performed at design time) to on-line (i.e. performed during system operation). Designs will be fabricated in silicon to demonstrate the impact of our research, and to enable real-time experimentation.

This project will have two main areas of impact: (1) in the design of next-generation embedded systems, and (2) in the realization of system-on-chip solutions for free-space optical communications. Our work in system synthesis we will enable the optimization of systems that would previously have been considered impractical. If successful, the project will also provide new design tools that will reduce NRE costs for embedded systems, and open up new application areas. The beneficiaries of this will be the embedded systems industry, from processor IP companies and compiler vendors, to fabless semiconductor companies and system integrators who build electronic devices for use in consumer, automotive, medical, telecommunications and energy industries. By applying dynamic adaptation to embedded systems we hope to solve the fundamental problem of how to cope with on-chip variation at silicon technologies below 65nm. At present this is an unsolved problem, requiring manufacturers to design-in expensive performance margins. Potential beneficiaries will be any future user of a battery-operated device, who will see better performance and longer battery life. The worldwide economic and environmental benefit of a switch to LED lighting is huge, and will drive the update of LED lighting. If this project is able to deliver a system-on-chip solution capable of high bandwidth digital communication through LED-based visible light this would have a far-reaching impact. Such LED light fittings would operate as both sources of low energy lighting and optical wireless access points. This would have a huge impact across a wide range of end-user products spanning the domestic, business, medical, and transportation domains. If the availability of VLC stimulates LED lighting uptake, then a potential future environmental benefit could be a significant reduction in CO2 emissions. This project will also extend and help to sustain the UK skill base in high-performance processor design and nanometre-scale silicon implementation. This project will benefit the UK skills base by training new doctoral students in these highly-specialized skills. The project contains a 10-point plan for maximizing the impact of the research: 1. We shall build demonstrator systems capable of showcasing the theories and algorithms underpinning our work. 2. In the final year of the project we will organise an Innovation Workshop, in order to disseminate our research results to UK and European SMEs. 3. We will engage with potential industrial beneficiaries, to share technologies for research purposes during the project. 4. We will leverage our recent experience in technology licensing to ensure that new technologies emerging from our research are transfered to industry. 5. The formation of a spin-out company will also be considered as a route to industrial exploitation of the VLC demonstrator. 6. We will continue to use online media to communicate to the academic community via http://groups.inf.ed.ac.uk/pasta/ 7. Postgraduate skill sets will be enhanced through training in nanometre-scale chip design. 8. To maximize the academic impact we shall publish our research in the most respected journals and the top conferences in the area. 9. Elements of the demonstrator platform will be offered to academic collaborators to stimulate exchange of ideas. 10. To maximize the academic benefit of our work we shall promote bilateral meetings between our group and others. The timescales for realising these benefits range from 1 to 5 years. The technology demonstrators will act as proof-of-concept, reducing the time needed to mature the ideas before further exploitation to a year or two. The economic benefits of LED-based communications will be realised when uptake grows, which is impossible to predict. However, these devices are driven by Moore's law, suggesting rapid adoption and potential for widespread use within a few years.