The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units (2008)
Attributed to:
Reconfigurable Architectures for Floating Point Applications
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1155/2008/736203
Publication URI: http://dx.doi.org/10.1155/2008/736203
Type: Journal Article/Review
Parent Publication: International Journal of Reconfigurable Computing