Formal Design and Verification of an Asynchronous SRAM Controller (2017)

First Author: Khomenko V
Attributed to:  A4A: Asynchronous design for analogue electronics funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/acsd.2017.12

Publication URI: http://dx.doi.org/10.1109/acsd.2017.12

Type: Conference/Paper/Proceeding/Abstract