Advanced layout techniques for high-speed analogue circuits in 28 nm HKMG CMOS process (2018)
Attributed to:
Silicon Photonics for Future Systems
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1049/el.2017.4453
Publication URI: http://dx.doi.org/10.1049/el.2017.4453
Type: Journal Article/Review
Parent Publication: Electronics Letters
Issue: 8