Language and Hardware Acceleration Backend for Graph Processing
Attributed to:
Event-based parallel computing - partially ordered event-triggered systems (POETS)
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1007/978-3-030-02215-0_4
Publication URI: http://dx.doi.org/10.1007/978-3-030-02215-0_4
Type: Book Chapter
Book Title: Languages, Design Methods, and Tools for Electronic System Design - Selected Contributions from FDL 2017 (2019)
Page Reference: 71-88