SElf-timed DATapath synthEsis (SEDATE)

Designing chips in deep-sub micron technologies is becoming increasing difficult. Parameter variations in fabrication processes mean that pre-determining a safe operating clock-rate is often over cautious. Self-timed circuits eliminate the global controlling clock in favour of circuits which are self-timed and which operate in response the availability of valid data. In the past, the design of such circuits has been difficult but in the last 10 years, great advances have been made in tools for the automatic synthesis of self-timed circuits. However, these automatic tools are best suited to control circuits or to low performance systems.This work will develop novel algorithms for the automatic synthesis of self-timed datapaths and will embed these tools in a framework that will allow a designer to choose from a variety of self-timed implementation design styles. A designer will be able choose from a range of implementations / from those that are completely insensitive to delays within components to those which are aggressively-timed using relative timing constraints based on actual layout parameters. Design-for-test techniques and relative timing constraints will be fully exploited by incorporating them into the datapath architecture. The focus of the proposed research will be the automated generation of self-timed datapath structures such as pipelines and low-latency combinational blocks targeted at standard cell libraries.