Ferroelectrics for Nanoelectronics (FERN)

The evolution of silicon technology since the 1960's has focussed on doubling performance and functionality every 18-24 months through miniaturization. Critical dimensions measured in tens of nanometres are now common place and billions of components connected by miles of wiring can be packed onto a wafer no larger than a thumb nail. Today the focus is shifting away from more scaling (called more Moore after the founder of Intel, Gordon Moore) towards increasing functionality through the introduction of mixed technologies on silicon (called more than Moore). This project investigates the incorporation of ultra thin ferroelectric materials into silicon nanoelectronics and two of its many applications.Capacitance is the rate of change of charge with voltage. It is the defining property of capacitors which are necessary in many electronic systems but are relatively large. Ferroelectrics can shrink capacitors by three orders of magnitude, because their electric permittivity is so high. More than that, their capacitance can be made to vary depending on the applied voltage so very small and tunable capacitors can be made, which can find applications in hand held electronics products in order to reduce power consumption. If they could be integrated onto a silicon microchip there would be further space savings. Thin layers are expected to produce even higher capacitance. However there is evidence that capacitance starts to reduce below 50 nm as dead layers are said to form near the interface with electrodes, but this may be an interface effect which can be lessened through engineering. Recently there has been experimental evidence that effective negative capacitance can be seen in ultra-thin ferroelectric films. If such material can be incorporated into a transistor then it would be able to reduce the voltage needed to switch a transistor between its on and off states (the sub-threshold slope). This would transform silicon technology, allowing a new generation of more powerful single core processors. Modern computers have dual or multi-core processors. A single core processor would generate too much heat but is still desirable for many applications. Capacitance places a lower limit on the sub-threshold slope. The consequence is that transistors need a larger applied voltage to be on and/or will leak current and so can never be fully switch off. This leads to increased power loss and heating as more transistors are crammed onto the same area of silicon, which limits component density. Integrating a ferroelectric film with negative capacitance into the gate of a transistor would reduce the overall capacitance and thus the sub-threshold swing. The need to understand and produce high quality ferroelectric ultra-thin films is imperative for each of these applications. Atomic Layer Deposition (ALD) at Newcastle and Pulsed Laser Deposition (PLD) at Imperial College will be used to deposit thin films of the ferroelectric materials barium titanate (BTO) and barium strontium titanate (BST). Both allow deposition thicknesses with atomic level precision. Extensive characterisation is needed to assess quality of these ferroelectric films. First principles computer simulation will be used to gain a better understanding of the films and to direct experiments. The deposition and thermal parameter space will be mapped to identify best ferroelectric properties for given constraints laid down by the silicon fabrication. Transistors will be made incorporating the best ferroelectric films to confirm the reduction in sub-threshold slope. Ferroelectric capacitors integrated onto silicon will be demonstrated, quantifying the capacitance increase per unit area and examining the fabrication constraints needed to maintain high transistor performance. This will also help identify integration issues, which also include equipment contamination and the development of ferroelectric etches.

The RAs and PG student trained will have the opportunity to develop excellent analytical, research and communications skills. Such people have previously gone on to work as permanent academic staff, in industry, in finance and in government research labs. The project will offer other RA's and PG students an opportunity to benefit from working on closely related topics in the area of thin film ferroelectrics and it is anticipated that this will boost the activity to benefit all. UK companies spanning the supply chain for high performance integrated circuits will gain competitive advantage. The primary benefits will be proof of concept for new types of semiconductor devices using ferroelectric thin films and the reduction of risk for development and manufacture of products using these devices. Materials companies benefit from expertise within this consortium and IP generated. Knowledge gained will accelerate their progress in producing high quality films for many applications. They can license the recipes for deposition of ferroelectric thin films adding value to their deposition system. They will benefit from the collaboration, especially characterisation and device data which will reassure customers. Mixing silicon with ferroelectrics for high permittivity voltage controlled capacitors will have the benefit of allowing single chip solutions where previously several components may be necessary. Using ferroelectric films to reduce transistor sub-threshold slope is high risk but has the potential for enormous benefits. The exponential increase in microchip leakage power and heating, as critical dimensions reduce and transistor count increases has halted single core processor evolution in favour of multiple core processors in order to have effective thermal management. A reduction in power consumption by integrated circuits must be of global benefit to the environment, since almost every appliance uses some silicon technology. Beneficiaries will include not only the semiconductor manufacturers, circuit designers and product manufacturers, but all of us who use their products. Ferroelectrics are also piezoelectric and pyroelectric and so a range of intelligent sensor/actuator systems might be envisaged. While the UK does not at present have state of the art silicon manufacturing, it is likely that in future UK based companies will partner with overseas semiconductor foundries for the supply of part-processed wafers (the transistors and some interconnect metallisation) which can be completed integrating a variety of mixed technologies (such as thin film ferroelectrics for tunable capacitors) to create IP intensive products of high added value. This may be particularly appropriate for partnering within the EU where it can make economic sense to share expensive semiconductor foundries. Publication of research in high quality journals and at leading international conferences is crucial and will continue. The industrial steering group will be a means of two-way communication and engagement between this academic project and the commercial sector. National electronics networks like Si Futures, UKDF and EU networks like Sinano will be accessed. Press releases to the trade press will also be used to announce the project and to publicise breaking news as it develops. The research will feature on web pages of the two universities. The quarterly management meetings will have a standing item on potential impact of research. Promising strands of research will be pursued and our steering group members will be approached for additional guidance. Patents will be sought where possible prior to publication of the research. Both PIs have previous experience of knowledge transfer to industry. Both universities have excellent media staff to help with communication.