Quantum Simulations of Future Solid State Transistors

Computers and electronic gadgets, such as the iphone, have transformed modern life. The silicon transistor is at the core of this revolution, having been continuously made faster and smaller over the last forty years. In a chip, millions of them are squeezed into an area the size of a pinhead, switching a billion times in one second. Transistor size has now reached nanometre dimensions; one nanometre is only ten time larger than an atom. Moore's law, which dictates that transistor size halves every two years and is the driving force behind the success of the electronics industry, has come to a halt. The happy and easy days of transistor scaling are now gone. Quantum mechanical laws conspire against transistor function making it leak when switched off and generating poor electrical control. Also, our inability to control the precise atomic structure of interfaces and chemical composition during fabrication makes transistors less predictable. Hence semiconductor companies are searching for alternative, non-planar (multigate) transistor architectures and novel devices such as nanowires, nanotubes, graphene and molecular transistors, which will ultimately break through the nano-size barrier resulting in a completely new era of miniaturization. There is a significant gap between our ability to fabricate transistors and to predict their behaviour.The simulation and prediction of the silicon transistor has become an vital mission. Current planar transistor architecture presents serious problems in scalability regarding leakage and controllability. Transistors of nanometre dimensions are more vulnerable to the atomic nature of matter than their previous cousins of micrometre dimensions. Furthermore, at nanoscales heat transfer is a source of heat death for novel transistor applications due to the decrease of thermal conductivity. Within this context I propose to develop a Quantum Device simulator, with atomic resolution that will enable the accurate prediction of present and future transistor performance. The simulator will deploy a quantum wave description of electron propagation, treating the interaction of electrons with crystal lattice vibrations (heat) at a fully quantum mechanical level. It will have the capability of describing the electron interactions with the roughness of the semiconductor/dielectric interface and with each other under the effect of a high electric field. Devices will be properly tested and optimised regarding materials, chemical composition and geometry without the high costs implicit in fabrication. A wide range of transistors will be explored from planar, non-planar and novel. This is timely as existing computer design tools lack predictive capabilities at the nanoscale and the industrial build-and-test approach has become prohibitively costly. Efficient quantum-models/algorithms/methodologies and tools will be developed.These are dynamic times as device dimensions move closer to the realm of atoms, which are inherently uncontrollable. In this regime two streams collide: the classical and quantum worlds making the need for new regularities and patterns vital as we strive to conquer nature at this scale. This offers exiting opportunities to merge an engineering top-to-bottom approach with a physics bottom-up approach. As 21st century environmental concerns rise, the need for greener technology is increasing. My proposal addresses the lowering of power consumption, raw material reductions delivering more functionality and the provision of a cheaper way to assess new design technologies. Collectively, these will help companies to provide a greener alternative to consumers.

The main beneficiaries will be the semiconductor industry (SI), nano-electronic fabrication centres, TCAD companies and spinout companies for TCAD software development. Others include UK HEIs and the general public. It is intended to develop efficient and predictive simulation tools for nano-electronics, which will provide cheaper assessments and design options for future technologies and consequently society, as a whole, will benefit from the availability of economical electronic products with greatly enhanced functionality and performance. How they will benefit? As the SI is urgently looking for new devices, which can successfully extend CMOS technology into sub-10 nanometer dimensions, the proposed simulation framework will create a virtual computational lab for SI to test and optimise new devices with regard to materials and architectures. It will contribute to the quantitative estimation of variability, currently a major hindrance in the downscaling of devices and their integration in large computer chips. Our tools will identify new device concepts and architectures that are less susceptible to variability. Dissipation and power consumption are key challenges in the quest for miniaturization and compact integration. Heat dissipation will be addressed in a multi-scale simulation approach, from microscopic nanostructures to the surrounding macroscopic environment, making the assessment of heat transfer and generation quite accurate. This will be a valuable asset for the microelectronics industry making it possible to design power saving devices. As the UK lacks the chip manufacturing capabilities of large companies in the USA and the Far East, the development of TCAD simulation software for devices and circuits offers a pathway into the multibillion-dollar SI. The development of these quantum device simulation capabilities and expertise is unique the UK and will maintain UK competitiveness in nanoelectronic TCAD software and will help to attract additional international industrial funding for the UK economy. Emerging British TCAD spin-out companies will have a nutritious arena for growth and will be able to adapt and service the More than Moore future scenario of nano-electronics, where modelling will be dominated by the individual interactions of atoms and electrons combined with the existing macroscopic models. Commercially there is ample opportunity for our proposed simulation tools, as no QM device simulation tools exist in the market. These tools also have the potential to be used for research and education purposes in HEI's. What will be done to ensure benefits? The Glasgow Modeling Group already has extensive contacts through present and previous research contracts with major semiconductor multinationals including: Intel, IBM, NXP, Hitachi, Toshiba and Freescale. This allows for a fruitful dissemination and sharing of research within these groups. My link with The Nano Research Group in Southampton (proposal partner) will permit the sharing of optimised nanostructures and potential novel materials with their collaborators. Our partner The Swiss Federal Institute of Technology operates a nano-lab, which fabricates ultra-small devices. They have acknowledged the importance of the proposed modeling tools and have expressed a commitment to use them in guiding design and fabrication. We intend to set up an interactive web site to promote engagement in science for young people. It will contain do it yourself simple simulations of gadget functions, ranging from simple to challenging models with an emphasis on the underlying physical principles and practical applications. We will proactively report findings at international conferences, where companies have a major presence and are the main sponsors. The publication of our findings in high impact journals will guarantee the dissemination of the results to all corners of the semiconductor and electronics industries.