Power-Adaptive Computing: Run-Time Management Design on FPGA SoC Devices

Traditional low-power design methodologies of embedded systems have focused on delivering performance-driven designs, where energy savings are achieved by relaxing execution time of tasks, while meeting the real-time deadlines. Conventional design strategies cannot longer ensure the computational certainty in emerging ubiquitous systems operating under varying levels of power, such as seen in ambient energy sources. Due to dynamic power behaviour, the stability and the computational progress of systems cannot be guaranteed, particularly when re-occurring power fluctuations or insufficient power budgets can terminate the completion of tasks and degrade the quality of applications. Therefore, this necessitates to design new runtime management solutions, which would allow to design versatile systems, where software and hardware handles are capable of effectively converting the available energy into computing power and guarantee task retention or completion under dynamic power profile.

Heterogeneous CPU-GPU based systems can achieve various performance and energy trade-offs, but when the energy is scarce, the same level of functionality can be achieved through highly customized hardware, such as FPGAs or ASICs. The increasing capabilities of high-level synthesis tools for logic design and shorter application development time makes FPGA SoCs appealing for custom designs. Offline power estimation tools allow to determine probabilistic system power consumption by simulating circuits. However, such approach cannot provide enough information about system's power behaviour at run-time. Complex designs require in-depth knowledge about sub-system level power usage. Therefore, provided with such information at high-level application layer and combined with adaptive run-time algorithms together with power management techniques, it would facilitate the design of energy-efficient and power-adaptive applications.
The key of this research is to establish an intelligent power-adaptive run-time management, which autonomously makes computing decisions in order to mitigate the computational uncertainties and warrant continuous functionality modulated by the incoming levels of power. For this purpose, the power-awareness feature will be introduced by analysing and modelling data obtained from a built-in hardware monitors, in order to formulate the power budgets. The decision to schedule computing tasks at run-time will be facilitated using machine learning algorithms coupled with power management techniques, such as voltage-frequency scaling. The research project is intended to develop a tool to support the design of power-adaptive systems, where the computing actions are governed by the run-time routines to modulate future computations within the energy or power constrain.