A comparison of AArch64 and RISC-V through accurate simulation

This project falls under the EPSRC architectures and operating systems research area.
Arm's AArch64 instruction set architecture (ISA) is currently establishing itself as a key alternative to x86 systems in the high performance computing (HPC) and cloud fields. This is most notably seen by its recent use in the A64FX chip, used within Fugaku, the most powerful supercomputer in the world up until June 2022 [1]. As a reduced instruction set computer (RISC), a natural competitor is RISC-V. Having been recently developed at UC Berkley, this open source ISA is starting to gain traction for use in real world applications due to it being simple, free to use, and open to modification, all features not provided by Arm's instruction set.
Large technology companies such as Google and Amazon are now moving towards the use of their own, in-house silicon for use in their cloud data centres. One of the first and most fundamental decisions to be made when designing these systems is the ISA, as this can affect every other part of a chip's microarchitecture. But currently, there is no objective data comparing multiple instruction sets, meaning these decisions must be made using more subjective metrics rather than hard evidence.
One of the initial aims of my research is to gain objective data allowing for a fair comparison of AArch64 and RISC-V. Firstly, I will conduct experiments into the instruction counts needed to run a range of HPC codes targeted by many commonly used compilers. As a follow up to this, I will determine if this difference in instruction count effects the time taken to run these codes on modern, high performance, out of order, superscalar processors.
To do this, I will help develop SimEng [2]; a fast, accurate, easily modifiable, open source processor simulator currently in development by the University of Bristol HPC research group. A simulator with all of these qualities has, up until now, not been openly available. Currently, within the field, there are two alternatives for accurate processor simulation: in-house simulators, which do not provide easily reproducible results; or Gem5 [3], which is often hard to modify and has slow simulation times. SimEng addresses these issues, allowing for easily gained and reproducible results.
My aim is to set up a simulation using the same microarchitectural backend with different front ends for each respective ISA. Running many different codes compiled to each ISA through this simulation will provide a fair comparison of the two ISAs when implemented in modern state-of-the-art processors. An experiment that, without SimEng, would have been very difficult to conduct but will provide invaluable data for tech companies informing their decisions about the next generation of cloud and HPC systems.
This work is partially funded by Huawei, who are helping to support rv32 within SimEng.
1. [online] https://www.top500.org/lists/top500/2021/11/
2. [online] https://github.com/UoB-HPC/SimEng
3. [online] https://www.gem5.org/