Advanced synthesiser techniques for mobile communications.

Lead Research Organisation: University College London
Department Name: Electronic and Electrical Engineering


Modern communications products, from TV sets to mobile phones, universally use a circuit known as a frequency synthesiser to generate a range of frequencies to allow the product to tune to different channels. In many applications, particularly mobile communications, these synthesisers need to produce very pure signals and simultaneously be able to change channels rapidly. These requirements are becoming increasingly demanding and often entail the use of multiple synthesiser loops in order to achieve the desired performance. More recently, a technique known as fractional-N synthesis has been developed to achieve this function using just a single synthesiser - a single-loop solution. This can tune very quickly, but tends to be noisy and, as a result, more advanced techniques have been applied, particularly sigma-delta modulation, to attempt to control this noise. However, there are still problems with this approach in terms of phase noise (a type of random noise) and discrete fractional spurs (individual tones).The proposed research involves investigation of three separate techniques, each originating from the applicants at UCL, to improve the performance of single-loop frequency synthesisers with the aim of rivalling or exceeding that of current multi-loop systems. The benefits of this would be a simplified, more compact and more economical implementation offering the same high performance. Since these circuits are very widely used, the commercial impact could be considerable. The first technique, known as stored-sequence synthesis, involves mimicking the behaviour of conventional sigma-delta fractional-N synthesisers by calculating the required bit sequences used to control the loop divider and storing them in memory. This is then read out at very high speed to produce the desired division ratio and hence channel frequency. The high speed and ability to generate and optimise the bit sequences off-line, offer major advantages in spectral purity and tuning speed and should provide an order of magnitude improvement over existing designs. The second part of the proposed project builds on our recent pioneering theoretical work on intermodulation effects in fractional-N synthesisers, in which we have discovered that a combination of natural phenomena (intermodulation and aliasing) are able to produce a family of discrete spurs at exactly the same frequencies as those due to a well known mechanism in a different part of the system, the modulator. This suggests that the phenomenon we have discovered may be an important and fundamental limitation on performance that has so far been completely overlooked; we would like to compare our theoretical work with experimental results from a carefully-designed test circuit to determine the true significance of this mechanism. This work may offer the opportunity to control the effects of such intermodulation and so improve performance. The final aim of the proposed research is to apply our experience in non-linear modelling of electronic systems, particularly sigma-delta ADCs (the subject of a previous EPSRC award) and chaos in PLLs, to develop a generic set of tools with which to obtain optimised fractional-N frequency synthesiser modulator designs and thus provide a scientific solution to what is currently something of a 'cut and try' design process.


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