Energy Efficient Networks-on-Chip for Dynamically Reconfigurable Computing Platforms.
Lead Research Organisation:
University of Manchester
Department Name: Computer Science
Abstract
The purpose of this work is to investigate an on-chip network fabric that will enable future reconfigurable computing systems integrating tens or hundreds of processing tiles implementing embedded microprocessors, intellectual property cores, reconfigurable fabrics, dedicated local memories and DSP functionality. The reconfigurable NoC fabric will direct the effective communication and exchange of data among the multiple processing tiles and enable fault-tolerance and very high communication bandwidths with low-latency and low energy consumption. The processing tiles will morph their functionality and operation point based on the application demands.
People |
ORCID iD |
Douglas Edwards (Principal Investigator) |
Publications
Song W
(2011)
Routing of asynchronous Clos networks
in IET Computers & Digital Techniques
Song W
(2011)
Asynchronous spatial division multiplexing router
in Microprocessors and Microsystems
Song W
(2010)
An Asynchronous Routing Algorithm for Clos Networks
Wei Song
(2010)
A low latency wormhole router for asynchronous on-chip networks
Wei Song
(2009)
Adaptive stochastic routing in fault-tolerant on-chip networks