The Reduceron: high level symbolic computing on FPGA

Symbolic computing is a key technology with programs often written in very expressive high level languages. The Reduceron is a custom processor for executing such symbolic programs by a technique called graph reduction. It is built on an FPGA (Field-Programmable Gate Array), a medium that allows rapid exploration of alternative designs. The current prototype was developed in just 2--3 months as a case-study in the closing stages of a PhD. Early results are sufficiently promising that we propose a 15-month feasibility study researching the potential of a special-purpose processor based on an advanced Reduceron. Results will be immediately applicable in FPGA-based systems and could inform the future design of a SPU (Symbolic Processing Unit) analogous to current highly successful GPUs for graphics.