Programmable Fabrics and Spatial Compilers
Lead Research Organisation:
University of Cambridge
Department Name: Computer Science and Technology
Abstract
Advances in fabrication technology will soon provide computer architects with an almost limitless supply of transistors. This technology scaling could permit thousands of individual processor cores to be integrated onto a single chip. In fact, many assume that these ``manycore architectures offer a panacea in terms of performance and scalability. Unfortunately, roadmaps built upon such an assumption often fail to consider the fundamental shift in design trade-offs that will take place in the longer term. It is the goal of this project to use a far more open-ended strategy to explore viable processor designs. We aim to investigate how key features of ASIC, FPGA and multicore approaches can be combined to produce the most apposite architectures. We call solutions from this region of the architectural design space programmable fabrics . These will be targeted by novel compilers with the ability to optimise program execution under a range of physical constraints. Unlike compilers for centralised uniprocessors, we expect to incorporate features from logic synthesis and place-and-route tools. The aim of this proposal is to highlight the need to explore longer term limits to performance and to evaluate a family of potential architectural solutions.
Organisations
People |
ORCID iD |
Robert Mullins (Principal Investigator) |
Publications
Bates D
(2014)
Exploiting Tightly-Coupled Cores
in Journal of Signal Processing Systems
Bates D
(2013)
Exploiting tightly-coupled cores
Bates Daniel
(2014)
Exploiting tightly-coupled cores
Description | The project developed and explored a new way of constructing power-efficient many-core processors. The key idea was to build a flexible sea of tightly coupled processors that could offer a wide-range of implementation opportunities in order to best exploit the characteristics of a particular application (e.g. availability of different forms of parallelism, communication patterns, memory requirements etc.). A significant amount of simulation and compiler infrastructure has been built to date. Initial results demonstrate that many different forms of parallelism can be exploited efficiently. We have been able to generate both performance and power numbers in order to make direct comparisons to existing processors. The work is continuing as part of a larger ERC funded project. This will include the fabrication of a test-chip. A collaboration with an industrial partner is currently ongoing (2016). |
Exploitation Route | It is hoped that the approaches we are exploring and the results we are producing will ultimately influence the design of commercial multiprocessors and system-on-chip designs. Current work with an industrial partner is promising in this respect. The current ERC funded phase of the project will produce test chips to demonstrate the key advantages of the approach. |
Sectors | Digital/Communication/Information Technologies (including Software) |
URL | http://www.cl.cam.ac.uk/~rdm34/loki/ |
Description | The research continues as a larger 5-year ERC project (2013-2018). We are also currently (2016) taking part in an industrially funded project to explore the use of the processor in machine-learning applications. |
Description | Industrial funding |
Amount | £133,000 (GBP) |
Organisation | Samsung |
Sector | Private |
Country | Korea, Republic of |
Start | 11/2015 |
End | 09/2016 |
Description | SPEAR: Specialisable, Programmable, Efficient and Robust Microprocessors |
Amount | £1,000,959 (GBP) |
Funding ID | 306386 |
Organisation | European Research Council (ERC) |
Sector | Public |
Country | Belgium |
Start | 03/2013 |
End | 03/2018 |