Software development support for DiRAC
Lead Research Organisation:
University of Edinburgh
Department Name: Sch of Physics and Astronomy
Abstract
We propose to partially mitigate the shortfall in projected DiRAC computing resources over the next year, arising from the delay to DiRAC-3, by continuing a code optimisation effort to accelerate DiRAC's scientific codes on current architectures, and which will also give a sustained long term benefit to scientific throughput on future machines. The effort will be used to provide profiling, benchmarking and optimisation services to maximise scientific return from the DiRAC by ensuring the most efficient use of computing resources possible. This represents continuation of a successful first year of such effort supported by the DiRAC Technical Working Group grant and with additional support from the University of Edinburgh. The first year of effort focused on the representation of the DiRAC workload as benchmarks to assess future supercomputing needs, and there have been significant benefits to the community arising from this activity. These included discovering vectorisation, caching optimisation, and MPI parallelisation strategies for codes of the VIRGO, UKQCD, UKMHD and Planck cosmology collaborations as examples.
DiRAC contains some areas of key international strength in high performance software engineering. DiRAC's expertise has been the foundation upon which the Alan Turing Institute has secured an internationally unique strategic partnership with Intel's HPC architecture group. There is an good opportunity for STFC to enable the rest of the DiRAC community to exploit the knowledge base.
DiRAC contains some areas of key international strength in high performance software engineering. DiRAC's expertise has been the foundation upon which the Alan Turing Institute has secured an internationally unique strategic partnership with Intel's HPC architecture group. There is an good opportunity for STFC to enable the rest of the DiRAC community to exploit the knowledge base.
Planned Impact
The proposed work will disseminate best practice in High Performance Computing software engineering throughout the theoretical Particle Physics, Astronomy and Nuclear physics communities in the UK. This will encourage the development of skills in the research community that are highly transferrable to the computations required for simulations in advanced manufacturing and computer aided design. Some level of the young researchers in the community leave academia each year as a natural part of the turnover that occurs in university sector research, especially given the limited number of research positions. The transfer of a portion of the research communities to other jobs carrying these skills is a key element that feeds UK industry from the space and satellite sector, through hard engineering and the financial sectors.
The DIRAC project has close ties with the highest levels of research and development in the computing industry. We designed a key component on the IBM BlueGene/Q system, as part of a unique Academic-Industrial joint project with IBM Watson Laboratory. The design has powered leading scientific computing installations around the world, from laboratories in the USA, Japan, Italy and Germany to our own national Hartree centre.
More recently DiRAC has been competitively awarded three Intel Parallel Computing Centres, won several international supercomputing awards, and developed a close codesign project with Intel on future HPC architectures. This latter effort promises the ability to influence a vast swathe of modern computing over the next five years. Such improvements in computing would impact all consumers of computional hardware, and in particular those doing numerical simulation such as the advanced manufacturing sector (e.g. Rolls Royce, BAE, Mclaren, Shell, Jaguar Land Rover), in addition to much of academic research in the physical sciences.
The Intel-Alan Turing Institute strategic partnership, with an HPC architecture team embedded in the ATI is built on this foundation of a deep collaboration with theoretical particle physicists. DiRAC's technical director is the codesign leader for the ATI and will transfer DiRAC's best practice codesign techniques to a number of other subject domains covering HPC and Data Science.
The Alan Turing Insitute, with DiRAC's codesign leader playing a central role is actively engaging with external partners, such as Intel, the MET office, Shell, and even Mclaren Racing, propagating vectorisation techniques developed in QCD codes to the important area of Finite Elements Modelling.
The present proposal provides resources for the theoretical particle physics, astronomy and nuclear physics communities to interact with the codesign knowledge centre. The opportunity to influence with sensible engineering decisions that optimise codes for products and products for codes is real. One example is a recurring element of computer architecture involves the tradeoff between throughput and accuracy of vectorised reciprocal square root instructions. These are a key element of the inverse square law that dominates the gravitational element of astronomy simulations. We have the opportunity to give definitive statements about the right balance to Intel.
Similarly we hope to provide useful information on the requirements for data motion, from the complexities of cache organisation and algorithms to interconnect requirements. Nowhere is this more pressing than addressing the enormous challenges presented by the Square Kilometre Array, perhaps a leading Big Data problem in the near future of scientific endeavour.
Our work can also lead to cross fertilisation into the nascent fields of machine learning and data science through the Alan Turing Institute.
The DIRAC project has close ties with the highest levels of research and development in the computing industry. We designed a key component on the IBM BlueGene/Q system, as part of a unique Academic-Industrial joint project with IBM Watson Laboratory. The design has powered leading scientific computing installations around the world, from laboratories in the USA, Japan, Italy and Germany to our own national Hartree centre.
More recently DiRAC has been competitively awarded three Intel Parallel Computing Centres, won several international supercomputing awards, and developed a close codesign project with Intel on future HPC architectures. This latter effort promises the ability to influence a vast swathe of modern computing over the next five years. Such improvements in computing would impact all consumers of computional hardware, and in particular those doing numerical simulation such as the advanced manufacturing sector (e.g. Rolls Royce, BAE, Mclaren, Shell, Jaguar Land Rover), in addition to much of academic research in the physical sciences.
The Intel-Alan Turing Institute strategic partnership, with an HPC architecture team embedded in the ATI is built on this foundation of a deep collaboration with theoretical particle physicists. DiRAC's technical director is the codesign leader for the ATI and will transfer DiRAC's best practice codesign techniques to a number of other subject domains covering HPC and Data Science.
The Alan Turing Insitute, with DiRAC's codesign leader playing a central role is actively engaging with external partners, such as Intel, the MET office, Shell, and even Mclaren Racing, propagating vectorisation techniques developed in QCD codes to the important area of Finite Elements Modelling.
The present proposal provides resources for the theoretical particle physics, astronomy and nuclear physics communities to interact with the codesign knowledge centre. The opportunity to influence with sensible engineering decisions that optimise codes for products and products for codes is real. One example is a recurring element of computer architecture involves the tradeoff between throughput and accuracy of vectorised reciprocal square root instructions. These are a key element of the inverse square law that dominates the gravitational element of astronomy simulations. We have the opportunity to give definitive statements about the right balance to Intel.
Similarly we hope to provide useful information on the requirements for data motion, from the complexities of cache organisation and algorithms to interconnect requirements. Nowhere is this more pressing than addressing the enormous challenges presented by the Square Kilometre Array, perhaps a leading Big Data problem in the near future of scientific endeavour.
Our work can also lead to cross fertilisation into the nascent fields of machine learning and data science through the Alan Turing Institute.
Publications

Acuto A
(2021)
The BAHAMAS project: evaluating the accuracy of the halo model in predicting the non-linear matter power spectrum
in Monthly Notices of the Royal Astronomical Society

Adamek J
(2020)
Numerical solutions to Einstein's equations in a shearing-dust universe: a code comparison
in Classical and Quantum Gravity

Agudelo Rueda J
(2021)
Three-dimensional magnetic reconnection in particle-in-cell simulations of anisotropic plasma turbulence
in Journal of Plasma Physics

Ahad S
(2021)
The stellar mass function and evolution of the density profile of galaxy clusters from the Hydrangea simulations at 0 < z < 1.5
in Monthly Notices of the Royal Astronomical Society

Al-Refaie A
(2021)
TauREx 3: A Fast, Dynamic, and Extendable Framework for Retrievals
in The Astrophysical Journal

Alioli S
(2021)
Four-lepton production in gluon fusion at NLO matched to parton showers
in The European Physical Journal C

Allanson O
(2020)
Particle-in-Cell Experiments Examine Electron Diffusion by Whistler-Mode Waves: 2. Quasi-Linear and Nonlinear Dynamics
in Journal of Geophysical Research: Space Physics

Allanson O
(2021)
Electron Diffusion and Advection During Nonlinear Interactions With Whistler-Mode Waves
in Journal of Geophysical Research: Space Physics

Almaraz E
(2020)
Nonlinear structure formation in Bound Dark Energy
in Journal of Cosmology and Astroparticle Physics
Description | DiRAC RSE's were hired by Intel and work with DiRAC team members to analyse the requirements of machine learning. We discovered the IEEE FP16 is not optimal for machine learning and that a new floating point format Bfloat16 is more effective. We coauthored a patent application with Intel |
Exploitation Route | We have demonstrated to Intel and coauthored a patent. It is being released as part of Intel's Cooperlake architecture for broad use. |
Sectors | Aerospace, Defence and Marine,Digital/Communication/Information Technologies (including Software),Electronics,Financial Services, and Management Consultancy,Transport,Other |
URL | http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=0&f=S&l=50&TERM1=Boyle&FIELD1=IN&co1=AND&TERM2=Kashyap&FIELD2=IN&d=PG01 |
Description | Yes. Indirectly DiRAC RSE'S were hired by Intel to work with me on Turing, and we coauthored a patent application with Intel on optimised 16 bit floating point instructions for machine learning. |
First Year Of Impact | 2018 |
Sector | Digital/Communication/Information Technologies (including Software),Electronics |
Impact Types | Economic |
Description | Intel ATI codesign project |
Organisation | Intel Corporation |
Department | Intel Corporation (Jones Farm) |
Country | United States |
Sector | Private |
PI Contribution | I lead the Alan Turing Institute / Intel codesign project. Two Intel engineers are placed in Edinburgh to work with me. We have developed profiling tools for machine learning packages and led to insight into the architectural requirements of deep learning that have been propagated to Intel. The tool has been used to study reduced precision floating point formats, and specific new instruction set extensions have been proposed to Intel. |
Collaborator Contribution | Two Intel engineers are placed in Edinburgh to work with me. We have developed profiling tools for machine learning packages and led to insight into the architectural requirements of deep learning that have been propagated to Intel. The tool has been used to study reduced precision floating point formats, and specific new instruction set extensions have been proposed to Intel. |
Impact | Paper with Intel MPI team. Multidisciplinary, particle physics, computing science and electronic engineering. |
Start Year | 2016 |
Description | Intel IPAG QCD codesign project |
Organisation | Intel Corporation |
Department | Intel Corporation (Jones Farm) |
Country | United States |
Sector | Private |
PI Contribution | We have collaborated with Intel corporation since 2014 with $720k of total direct funding, starting initially as an Intel parallel computing centre, and expanding to direct close collaboration with Intel Pathfinding and Architecture Group. |
Collaborator Contribution | We have performed detailed optimisation of QCD codes (Wilson, Domain Wall, Staggered) on Intel many core architectures. We have investigated the memory system and interconnect performance, particularly on Intel's latest interconnect hardware called Omnipath. We found serious performance issues and worked with Intel to plan a solution and this has been verified and is available as beta software. It will reach general availability in the Intel MPI 2019 release, and allow threaded concurrent communications in MPI for the first time. A joint paper on the resolution to this was written with the Intel MPI team, and the application of the same QCD programming techniques to machine learning gradient reduction was applied in the paper to the Baidu Research all reduce library, demonstrating a 10x gain for this critical step in machine learning in clustered environments. We are also working with Intel verifying future architectures that will deliver the exascale performance in 2021. |
Impact | We have performed detailed optimisation of QCD codes (Wilson, Domain Wall, Staggered) on Intel many core architectures. We have investigated the memory system and interconnect performance, particularly on Intel's latest interconnect hardware called Omnipath. We found serious performance issues and worked with Intel to plan a solution and this has been verified and is available as beta software. It will reach general availability in the Intel MPI 2019 release, and allow threaded concurrent communications in MPI for the first time. A joint paper on the resolution to this was written with the Intel MPI team, and the application of the same QCD programming techniques to machine learning gradient reduction was applied in the paper to the Baidu Research all reduce library, demonstrating a 10x gain for this critical step in machine learning in clustered environments. This collaboration has been renewed annually in 2018, 2019, 2020. Two DiRAC RSE's were hired by Intel to work on the Turing collaboration. |
Start Year | 2016 |
Title | FP16-S7E8 MIXED PRECISION FOR DEEP LEARNING AND OTHER ALGORITHMS |
Description | We demonstrated that a new non-IEEE 16 bit floating point format is the optimal choice for machine learning training and proposed instructions. |
IP Reference | US20190042544 |
Protection | Patent application published |
Year Protection Granted | 2019 |
Licensed | Yes |
Impact | We demonstrated that a new non-IEEE 16 bit floating point format is the optimal choice for machine learning training and proposed instructions. Intel filed this with US patent office. This IP is owned by Intel under the terms of the Intel Turing strategic partnership contract. As a co-inventor I have been named on the patent application. The proposed format has been announced as planned for use in future Intel architectures. This collaboration with Turing emerged out of an investment in Edinburgh by Intel Pathfinding and Architecture Group in codesign with lattice gauge theory simulations. Intel hired DiRAC RSE's Kashyap and Lepper and placed them in Edinburgh to work with me on Machine Learning codesign through the Turing programme. |
Description | Panel discussion on machine learning and future HPC Intel HPC developer conference. |
Form Of Engagement Activity | A formal working group, expert panel or dialogue |
Part Of Official Scheme? | No |
Geographic Reach | International |
Primary Audience | Industry/Business |
Results and Impact | Invited as panel expert on future of HPC and machine learning by Intel at their annual HPC developer conference attended widely by Industry and research lab sector. Note, Boyle second from left in photograph on the Intel web page linked below. |
Year(s) Of Engagement Activity | 2017 |
URL | https://www.intel.com/content/www/us/en/events/hpcdevcon/overview.html |
Description | Talk on MPI optimisation on Intel stand at Supercomputing 2017 |
Form Of Engagement Activity | A talk or presentation |
Part Of Official Scheme? | No |
Geographic Reach | International |
Primary Audience | Industry/Business |
Results and Impact | Decision influence: I Influenced Intel to modify, update and release optimisations to their MPI library for the Intel Omnipath interconnect. Coauthored a paper on this topic. |
Year(s) Of Engagement Activity | 2017 |
URL | http://inspirehep.net/record/1636204 |
Description | Talks presented on this activity at Intel Xeon Phi User Group conferences. |
Form Of Engagement Activity | A talk or presentation |
Part Of Official Scheme? | No |
Geographic Reach | International |
Primary Audience | Industry/Business |
Results and Impact | Presented work in several Intel Xeon Phi User Group meetings. |
Year(s) Of Engagement Activity | 2016,2017 |