A compiler for deep neural networks on reconfigurable platforms

Lead Research Organisation: Imperial College London
Department Name: Dept of Computing

Abstract

This project is about designing a compiler for deep neural networks, such as convolutional neural networks, on reconfigurable platforms, such as FPGA (Field-programmable gate array). This compiler will be able to automatically optimise the model with different computation configurations, understand the workload and efficiently deploy the model on reconfigurable platforms. Possible techniques that will be explored in this project include network architecture search, transfer learning, quantisation, polyhedral analysis, operator fusion, etc. A proposed working pipeline would be, the compiler takes an original model, explores possible architectural changes based on this model, analysis the workload and possible hardware designs of the optimised models, and generate the optimal design on FPGA. The expected outcome of this project will be a properly developed compiler and thorough evaluation on common deep neural network benchmarks.

Publications

10 25 50

Studentship Projects

Project Reference Relationship Related To Start End Student Name
EP/R512540/1 01/10/2017 30/09/2021
2021246 Studentship EP/R512540/1 01/10/2017 30/09/2021 Ruizhe Zhao