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Improved State Integrity of Flip-Flops for Voltage Scaled Retention Under PVT Variation (2013)

First Author: Yang S

Attributed to: Variation-Aware Test for NanoScale CMOS Integrated Circuits funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/tcsi.2013.2252640

Publication URI: http://dx.doi.org/10.1109/tcsi.2013.2252640

Type: Journal Article/Review

Parent Publication: IEEE Transactions on Circuits and Systems I: Regular Papers

Issue: 11