A Fast and Accurate Process Variation-Aware Modeling Technique for Resistive Bridge Defects (2011)
Attributed to:
Variation-Aware Test for NanoScale CMOS Integrated Circuits
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1109/tcad.2011.2162065
Publication URI: http://dx.doi.org/10.1109/tcad.2011.2162065
Type: Journal Article/Review
Parent Publication: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue: 11