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Gate-Sizing-Based Single $V_{\rm dd}$ Test for Bridge Defects in Multivoltage Designs (2010)

First Author: Khursheed S

Attributed to: Variation-Aware Test for NanoScale CMOS Integrated Circuits funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/tcad.2010.2059310

Publication URI: http://dx.doi.org/10.1109/tcad.2010.2059310

Type: Journal Article/Review

Parent Publication: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue: 9