Modeling the impact of process variation on resistive bridge defects (2010)

First Author: Khursheed S
Attributed to:  Variation-Aware Test for NanoScale CMOS Integrated Circuits funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/test.2010.5699230

Publication URI: http://dx.doi.org/10.1109/test.2010.5699230

Type: Conference/Paper/Proceeding/Abstract

ISBN: 978-1-4244-7206-2