System-level yield optimisation using hierarchical-based design flow (2009)
Attributed to:
Reliable Power Systems and Integrated Circuits
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1049/el.2009.0393
Publication URI: http://dx.doi.org/10.1049/el.2009.0393
Type: Journal Article/Review
Parent Publication: Electronics Letters
Issue: 12