Tunable CMOS delay gate with reduced impact of fabrication mismatch on timing parameters (2013)

First Author: Mroszczyk P
Attributed to:  Fine-Grain Parallel Cellular Processor Arrays in 3D Silicon Technologies funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/newcas.2013.6573595

Publication URI: http://dx.doi.org/10.1109/newcas.2013.6573595

Type: Conference/Paper/Proceeding/Abstract

ISBN: 978-1-4799-0618-5