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Tunable CMOS Delay Gate With Improved Matching Properties (2014)

First Author: Mroszczyk P

Attributed to: Fine-Grain Parallel Cellular Processor Arrays in 3D Silicon Technologies funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/tcsi.2014.2312491

Publication URI: http://dx.doi.org/10.1109/tcsi.2014.2312491

Type: Journal Article/Review

Parent Publication: IEEE Transactions on Circuits and Systems I: Regular Papers

Issue: 9