Fully self-aligned process for fabricating 100nm gate length enhancement mode GaAs metal-oxide-semiconductor field-effect transistors (2009)
Attributed to:
III-V MOSFETs for Ultimate CMOS
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1116/1.3256624
Publication URI: http://dx.doi.org/10.1116/1.3256624
Type: Journal Article/Review
Parent Publication: Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena
Issue: 6