📣 Try out the NEW Gateway to Research and let us know what you think.

We're looking for users to test the new service during August and September and share their feedback. Express your interest by completing this short form.

ROM to DSP block transfer for resource constrained synthesis (2007)

First Author: Morris G

Attributed to: Reconfigurable Architecture Design: An Optimization Approach funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1049/iet-cdt:20060016

Publication URI: http://dx.doi.org/10.1049/iet-cdt:20060016

Type: Journal Article/Review

Parent Publication: IET Computers & Digital Techniques

Issue: 1