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A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementation

First Author: Lopes A

Attributed to: Reconfigurable Architecture Design: An Optimization Approach funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1007/978-3-540-78610-8_10

Publication URI: http://dx.doi.org/10.1007/978-3-540-78610-8_10

Type: Book Chapter

Book Title: Reconfigurable Computing: Architectures, Tools and Applications (2008)

Page Reference: 75-86