Optimizing SDRAM bandwidth for custom FPGA loop accelerators (2012)
Attributed to:
Reliable Numerical Computation with Parallel Unreliable Technologies
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1145/2145694.2145727
Publication URI: http://dx.doi.org/10.1145/2145694.2145727
Type: Conference/Paper/Proceeding/Abstract
ISBN: 9781450311557