DFT Architecture With Power-Distribution-Network Consideration for Delay-Based Power Gating Test (2015)

First Author: Tenentes V
Attributed to:  Resilient and Testable Energy-Efficient Digital Hardware funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/tcad.2015.2446939

Publication URI: http://dx.doi.org/10.1109/tcad.2015.2446939

Type: Journal Article/Review

Parent Publication: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue: 12